The present disclosure relates to functional verification in general, and to generation and simulation of self modifying code, in particular.
Computerized devices control almost every aspect of our life—from writing documents to controlling traffic lights. However, computerized devices are bug-prone, and thus require a testing phase in which the bugs should be discovered. The testing phase is considered one of the most difficult tasks in designing a computerized device. The cost of not discovering a bug may be enormous, as the consequences of the bug may be disastrous. For example, a bug may cause the injury of a person relying on the designated behavior of the computerized device. Additionally, a bug in hardware or firmware may be expensive to fix, as patching it requires call-back of the computerized device. Hence, many developers of computerized devices invest a substantial portion of the development cycle to discover erroneous behaviors of the computerized device.
Functional verification is one method that may be employed to increase quality of the computerized device. Functional verification tries to check that the design of the computerized device is in accordance with requirements. One method of performing functional verification is by generating stimuli and injecting the stimuli to a simulation of the computerized device. Generation may be biased towards stimuli of a relatively high quality. Generation may be based on a test template, which comprises a definition of the various characteristic that the stimuli should have. The test template may be provided in a context-free formal language. The simulator may simulate execution of the computerized device based on a descriptive language describing the device, such as for example an Hardware Descriptive Language (HDL), SystemC, Verilog or the like. In some exemplary embodiments, online generators employ generation-simulation cycles, in which one or more instructions are generated and execution thereof is simulated. Based on the state of a reference model (i.e., the simulated state of the computerized device), successive instructions may be generated in the next cycle. In some exemplary embodiments, offline generators generate a complete test based on the test template, and thereafter a simulator is utilized to simulate the execution thereof. In an offline generator, the generation is not affected by the simulation process.
A System-Under-Test (SUT), such as a processor, an accelerator, or a similar processing device, may be capable of handling Self Modifying Code (SMC). An SMC is a set of instructions (e.g., a program) that, once loaded onto the SUT, may cause the SUT to modify the program by adding, deleting, modifying the set of instructions. In some exemplary embodiments, the SMC may determine a new instruction and add to the instruction